1. Field
The embodiments of the present invention relate to a specification verification program that verifies coverage of a requirements specification of a design object, such as a software or hardware product, against a design specification of the design object. The invention further relates to a computer-readable storage medium storing therein the specification verification program, a specification verification apparatus, and a specification verification method.
2. Description of the Related Art
At present, with increase and advances of software and hardware in regard to scale and multi-functionality, the verification task for providing the system quality assurance encounters increasing difficulty. Generally, two tasks are known to be necessary for providing the system quality assurance. One of the tasks is an assurance of correctness in design, and the other is an assurance of correctness in implementation.
Present-day verification/testing techniques are developed focusing attention on, in general, the latter “assurance of correctness in implementation”. As examples, there are provided techniques of the type that evaluates the degree of coverage of a test case, which is verified regarding whether a design object operates in conformity with a corresponding specification, thereby executing a comprehensive logic verification (see Japanese Patent Application Laid-Open (JP-A) No. 03-99228 and 2001-14365, for example).
Further, there are provided methods of the type that extracts verification properties of a design object on the basis of the implementation level, and evaluates the degree of coverage of the verification properties against a design specification of the design object, thereby to execute the comprehensive logic verification (see Y. Hoskote, T. Kam, P. H. Ho, and X. Zao, “Coverage Estimation for Symbolic Model Checking,” in Proc. of ACM/IEEE DAC, 1999, pp. 300-305; and X. Xu, S. Kimura, K. Horikawa, and T. Tsuchiya, “Transition-based coverage estimation for symbolic model checking,” in Proc. of ACM/IEEE, for example).
However, according to conventional techniques, such as described in JP-A-03-99228 and JP-A-2001-14365, no specific consideration is taken into “assurance of correctness in design”, which is one of the generally known tasks for providing the system quality assurance. In many cases, the specification is described in a natural language, and hence the assurance of correctness in design is checked in the manner of review of the design, that is, visual checking of the design.
As such, obscurity, inconsistency, omission (missing), and error of the specifications cannot be completely eliminated, so that many cases result in incorrect or fault designs. This causes frequent rectification operations due to fault verification processes, resulting in an increase in the work time of the verification process and hence in an increase in the work time of the design process.
According to the conventional techniques described in JP-A-03-99228 and JP-A-2001-14365, specification requirements are extracted as verification properties, and the degree of coverage with respect to respective outputs is evaluated. As such, it is necessary to perform a process of defining verification properties and observation signals. This requires, for example, much time and labor, resulting in an increase in the work time of the verification process and hence an increase in the work time of the design process.